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csmc keeps an intense and close collaboration with major electronic design automation (eda) vendors to jointly develop design kits with them. so we can meet our customer‘s  various design needs perfectly.

 reference flow





 physical verification tools

 tech. node process process description calibre assura argus
 0.11μm eflash p-sub, 1.5v/3.3v/5v √  
 0.13μm mixed-signal/rf p-sub,1.2v/3.3v including rf √  
 0.153μm mcu p-sub,5v including rf √  
 cmos p-sub,7v √  
 0.16μm logic  p-sub,1.8v/3.3v √  
 mixed-signal/rf p-sub,1.8v/3.3v, including rf √  
 0.18μm logic p-sub, 1.8v/3.3v √  
 mixed-signal/rf p-sub,1.8v/3.3v, including rf √ √ 
 hv p-sub, 1.8v/5v √  
 1.8v 18v vgs 18v vds hvmos process √  
 mcu p-sub, 3.3v/5v/6v √ √ 
 bcd p-sub, 3.3v/5v √  
 25vbcd p-sub,1.8v&5v vgs 25v vds non-epi bcd √  
 p-sub,1.8v&5v vgs 25v vds p-epi bcd √  
 eflash p-sub,1.8v&3.3v&5v √  
 sourcedriver 1.8v&18v √  
 3.3v&13.5v √  
 3.3v&18v √  
 bcd 7-30v scalable p-epi bcd db  √  
 db sbcd g2s 7v 80v process  √  
 db sbcd g2s 80v 120v process √  
 db sbcd g3 process √  
 ab sbcd g1 7v 30v process √  
 ab sbcd g1s process √  
 eeprom eeprom √  
 0.25μm bcd 5v vgs 25v vds 2p5m  √  
 5v vgs 12v/45v vds 2p5m √  
 30v60v √  
 1p4m salicide 5v analog  √  
 0.35μm flatcell p-sub,5v spqm, 0.7μm *0.7μm flatcell cell, single poly, 4 metal √ √ 
 p-sub,3.3v/5v, 0.7μm *0.7μm flatcell, single poly, √ √ 
 single metal
 p-sub, 3.5v/5v, 0.63μm *0.63μm flatcell, dual gate oxide √  
 mixed-signal p-sub,3.3v/5v  √  √
 otp mix otp dpqm 3.3v 5v  √  
 bcd 3.3v vgs 12v_15v vds √  
 logic g2 3.3v √  
 0.5feol/0.35beol mixed-signal 0.5feol/0.35beol  √  
 0.5feol/0.35beol 1.8ff/um^2 √  
 plain-poly, 3~5v √  
 0.5μm mixed-signal enhance analog for 5v √  
 p-sub,5v, with pip/high p2/lvt/depletion √ √ √
 p-sub,5v, with pip/high p2/lvt/depletion 1.8ff cpip √  
 hv p-sub,40v/25v process √ √ 
 p-sub,deep nwell 5v process √ √ 
 p-sub,5v/18v process   
 bcd 0.5um 15v(vgs)/15v(vds) dptm bcdmos process √ √ 
 0.5um 5v(vgs)/15v(vds) dptm bcdmos process √ √ 
 0.5um 5v(vgs)/25v(vds) dptm bcdmos process √ √ 
 0.5um 25v(vgs)/25v(vds) dptm bcdmos process √ √ 
 0.5um 5v(vgs)/40v(vds) dptm bcdmos process  √  
 0.5μm feol 0.6μm beol    
 p-sub,18v/20v thick_ox bcdmos process √ √ 
 p-sub,5v/20v thin_gox bcdmos process √ √ 
 p-sub,5v/40v thin_gox bcdmos process  √ √ 
 p-sub,25v/40v thick_gox bcdmos process  √ √ 
 0.6μm logic p-sub,5v,plain poly, before n-rom √  
 p-sub,lv,plain poly, before n-rom √  
 n-sub,5v,n-rom before plain poly √  
 mixed- signal p-sub, 5v, pip/high p2 √  
 p-sub, 5v, pip/high p2,lvt, depletion √  
 hv n-sub, 5v-18v √  
 1.0μm  mglv n-sub,1.5-5v √  
 n-sub,3.0-5v √  
 hv p-sub,5v/40v  √  
 p-sub,5v/40v, 0.5μm backend, and thick al2 is option √  
 p-sub,5v/25v, 0.5μm backend, and thick al2 is option(hv gox 600a) √  
 2.0μm 36v dn, nitride cap, 1m √  
 dn, nitride cap, p-, p , 1m √  
 18v (5μm tepi) dn,sin cap, 1m(5μm epi) √